1. Field of the Invention
This invention relates generally to memory cells array structures, and methods for writing and reading the memory cells. More particularly, this invention relates to spin-torque magnetic random access memory (MRAM) cells, array structures for spin-torque MRAM cells, and methods for writing and reading spin-torque MRAM cells.
2. Description of Related Art
The term Spin-RAM refers to a magnetic tunnel junction (MTJ) random access memory (RAM). In this context, the term “spin” refers to the angular momentum of electrons passing through an MTJ that will alter the magnetic moment of a free layer of an MTJ device. Electrons possess both electric charge and angular momentum (or spin). It is known in the art that a current of spin-polarized electrons can change the magnetic orientation of a free ferromagnetic layer of an MTJ via an exchange of spin angular momentum.
“A Novel Nonvolatile Memory with Spin-torque Transfer Magnetization Switching: Spin-Ram”, Hosomi, et al., IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. December 2005, pp.: 459-462, provides a nonvolatile memory utilizing spin-torque transfer magnetization switching (STS), abbreviated Spin-RAM. The Spin-RAM is programmed by magnetization reversal through an interaction of a spin momentum-torque-transferred current and a magnetic moment of memory layers in magnetic tunnel junctions (MTJs), and therefore an external magnetic field is unnecessary as that for a conventional MRAM.
Refer now to FIG. 1 for an explanation of spin-torque transfer switching (STS) in an MTJ element 5 as described Hosomi, et al. A spin-torque MTJ 5 element has two ferromagnetic layers, F1 10 and F2 15, and a spacer layer 20 between the ferromagnetic layers, F1 10 and F2 15. The ferromagnetic layers, F1 10 is a pinned magnetic layer. The spacer layer 20 is a tunnel barrier layer. The ferromagnetic layer F2 15 is a free magnetic layer. When a spin polarized electron 40 flows through the ferromagnetic layers, F1 10 and F2 15, the spin direction 42 rotates according to the directions of magnetic moment M2 55 and M1 50 respectively to the directions 43 and 44. The rotation of spin direction of the electrons in the ferromagnetic layers, F1 10 and F2 15 are the origin of a spin-torque, dM1/dt 47 and dM2/dt 45, to the magnetic moment M1 50 and M2 55. The given torque is large enough, magnetization of ferromagnetic layer F2 15 and thus the magnetic moment M2 55 is reversed. The magnetization of the ferromagnetic layers, F1 10 and F2 15 transforms from parallel to anti-parallel alignment. This changes the MTJ element 5 from a low resistance state to a high resistance state thus changing the logic state of the MTJ element from a first logic state (0) to a second logic state (1).
The voltage source 35 provides the programming voltage VPROG that generates the programming current iPROG that is reversed appropriately change the programming state of the MTJ element 5.
As illustrated in FIG. 2, an MRAM cell 100 consists of an MTJ element 105 and a Metal Oxide Semiconductor (MOS) transistor 110. The MTJ element 105 is composed of a pinned ferromagnetic layer 102 and a free ferromagnetic layer 104, and a tunnel barrier layer 103 as described in FIG. 1. The drain of the MOS transistor 110 is connected through a nonmagnetic layer to the pinned ferromagnetic layer 102. The free ferromagnetic layer 104 is connected to a bit line 115 and the source of the MOS transistor 110 is connected the source select line 120. The bit line 115 and source select line 120 are connected to the bipolar write pulse/read bias generator 125. The bipolar write pulse/read bias generator 125 provides the necessary programming current to the MTJ element 105 through the bit line 115 and the source select line 120. The direction being determined by logic state being programmed to the MTJ element 105.
The gate of the MOS transistor 110 is connected to a word line 130. The word line 130 is transfers a word line select voltage to the gate of the MOS transistor 110 to activate the MOS transistor 110 for reading or writing the logic state of the MTJ element 105. A sense amplifier 135 has one input terminal connected to the bit line and a second input terminal connected to a voltage reference circuit. When the word line 115 has the word line select voltage activated to turn on the MOS transistor 110, the bipolar write pulse/read bias generator 125 generates a bias current that passes through MTJ element 105. A voltage is developed across the MTJ element 105 that is sensed by the sense amplifier 135 and compared with the reference voltage generator to determine the logic state written to the MTJ element 105. This logic state is transferred to the output terminal of the sense amplifier 135 as to the data output signal 145.
Refer to FIG. 3 for a description of an array of MRAM cells 100. The MRAM cells 100 are arranged in rows and columns. The gate of the MOS transistor of each of the MRAM cell 100 on a row of the MRAM cells 100 is connected to a word line 200a, 200b, . . . , 200n-1, 200n to receive the word line select signal to activate the MOS transistor for writing and reading of a selected MRAM cell 100. One terminal of each of MTJ element of the MRAM cells 100 on a column of MRAM cells 100 is connected to a bit line 205a, 205b, . . . , 205m. The source of each MOS transistor of each of the MRAM cells 100 is connected to a source select line 210a, 210b, . . . , 210m. During a write operation, a programming voltage is transferred either from a selected bit line 205a, 205b, . . . , 205m through the selected MRAM cell 100 to the selected source select line 210a, 210b, . . . , 210m or from selected source select line 210a, 210b, . . . , 210m through the selected MRAM cell 100 to the a selected bit line 205a, 205b, . . . , 205m, dependent upon the logic state to be written to the selected MRAM cell 100.
The array structure of Hosomi, et al. as shown requires essentially two bit lines—the bit lines 205a, 205b, . . . , 205m and the source select lines 210a, 210b, 210m. This structure as described leads to an inefficient cell and MRAM cell 100 and array layout.
“Highly Scalable MRAM Using Field Assisted Current Induced Switching”, Jeong, et al, 2005 Symposium on VLSI Technology, 2005. Digest of Technical Papers, June 2005, pp. 184-185, describes an MRAM structure using current induced switching.
“Spin-Transfer Switching Current Distribution and Reduction in Magnetic Tunneling Junction-Based Structures”, Huai, et al., IEEE Transactions on Magnetics, October 2005, Vol.: 41, Issue: 10, pp.: 2621-2626, provides the results of studies into a spin transfer switching current distribution within a cell and switching current reduction at room temperature for magnetic tunnel junction-based structures with resistance area product (RA) ranged from 10 to 30Ω2 and TMR of 15%-30%.
U.S. Pat. No. 6,097,626 (Brug, et al.) teaches an MRAM device using magnetic field bias to suppress inadvertent switching of half-selected memory cells. The magnetic field bias is applied to half-selected memory cells during a write operation.
U.S. Pat. No. 6,130,814 (Sun) describes a magnetic switching device, includes two electrodes and a nanoparticle between the two electrodes having a magnetic moment. At least one of the electrodes includes a magnetic material which has a net spin polarization in its conduction band for injecting, into the nanoparticle, an electrical current including a net spin polarization for overcoming the magnetic moment of the nanoparticle upon selection of a predetermined magnitude for the electrical current.
U.S. Pat. No. 6,847,547 (Albert, et al.) provides magnetostatically coupled magnetic elements utilizing spin transfer. The magnetic element is configured to write to the free layers using spin transfer when a write current is passed through the magnetic element.
U.S. Pat. No. 6,865,109 (Covington) describes a magnetic random access memory having flux closure for the free layer and spin transfer write mechanism.
U.S. Pat. No. 6,980,469 (Kent, et al.) illustrates a high speed low power magnetic devices based on current induced spin-momentum transfer. The magnetic device comprises a pinned magnetic layer with a fixed magnetization direction, a free magnetic layer with a free magnetization direction, and a read-out magnetic layer with a fixed magnetization direction. The pinned magnetic layer and the free magnetic layer are separated by a non-magnetic layer, and the free magnetic layer and the read-out magnetic layer are separated by another non-magnetic layer. The magnetization directions of the pinned and free layers generally do not point along the same axis. The non-magnetic layers minimize the magnetic interaction between the magnetic layers. A current is applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information.
U.S. Pat. No. 7,006,375 (Covington) provides a method of writing to a magnetic random access memory by producing a magnetic field along a magnetically hard axis of a free layer of a magnetoresistive element; and passing current through the magnetoresistive element to change a direction of magnetization of the free layer by spin momentum transfer.
U.S. Pat. No. 7,009,877 (Huai, et al.) illustrates a three-terminal magnetostatically coupled spin transfer-based MRAM cell. The MRAM cell has a spin transfer driven element, disposed between a first and a second of the three terminals. A readout element is disposed between the second terminal and a third of the three terminals. The spin transfer driven element and the readout element each include a free layer. A magnetization direction of the free layer in the readout element indicates a data state. A magnetization reversal of the free layer within the spin transfer driven element magnetostatically causes a magnetization reversal of the free layer in the readout element, thereby recording the data state.
U.S. Pat. No. 7,102,920 (Perner, et al.) details a soft-reference three conductor magnetic memory storage device. The device has parallel electrically conductive first sense/write conductors and parallel electrically conductive sense conductors. The sense/write and second sense conductors provide a cross point array where soft-reference magnetic memory cells are provided in electrical contact with and located at each intersection. Parallel electrically conductive write column conductors substantially are proximate to and electrically isolated from the sense conductors. Sense magnetic fields orient the soft-reference layer but do not alter the data stored within the cell.
U.S. Patent Application 20060171198 (Saito, et al.) describes a spin-injection magnetic random access memory. The spin-injection magnetic random access memory includes a magnetoresistive element having a magnetic fixed layer whose magnetization direction is fixed, a magnetic recording layer whose magnetization direction can be changed by injecting spin-polarized electrons, and a tunnel barrier layer provided between the magnetic fixed layer and the magnetic recording layer. A bit line passes spin-injection current through the magnetoresistive element for generation of the spin-polarized electrons. A writing word line has an assist current passed through it for the generation of an assist magnetic field in a magnetization easy-axis direction of the magnetoresistive element. A driver/sinker determines a direction of the spin-injection current and a direction of the assist current.